A comprehensive study on the FIBL of nanoscale MOSFETs

Bing-Yue Tsui*, Li Feng Chin

*Corresponding author for this work

Research output: Contribution to journalArticle

30 Scopus citations

Abstract

Fringing-induced barrier lowering (FIBL) effect on nanoscale MOSFET is comprehensively examined. It is observed that by combining stack gate dielectric, conductive spacer, short sidewall spacer, and minimum gate/drain (G/D) overlap, the Ioff with a dielectric constant of (k) 100 is only 1.6 times higher than that with k = 3.9 when the gate length is 25 nm. The fully depleted silicon-on-insulator device shows even better FIBL immunity. It is concluded that although the FIBL effect can not be eliminated, it would not an issue beyond the 45-nm technology node.

Original languageEnglish
Pages (from-to)1733-1735
Number of pages3
JournalIEEE Transactions on Electron Devices
Volume51
Issue number10
DOIs
StatePublished - 1 Oct 2004

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