A comprehensive investigation of analog performance for uniaxial strained PMOSFETs

Jack Jyun Yan Kuo*, William Po Nien Chen, Pin Su

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

9 Scopus citations


This paper presents a comprehensive investigation of the analog performance for uniaxial strained PMOSFETs with sub-100 nm gate length. Through a comparison between co-processed strained and unstrained devices regarding important analog metrics such as transconductance to drain current ratio (gm/Id), dc gain, linearity, low-frequency noise, and device mismatch, the impact of process-induced uniaxial strain on the analog performance of MOS devices has been assessed and analyzed. Our results indicate that, although the drain current noise spectral density and drain current mismatch of the strained device under low gate voltage overdrive are increased because of the larger gate-bias sensitivity of carrier mobility, the strained device has almost the same low frequency and mismatch performance as the unstrained one at a given gm/Id. This paper may provide insights for analog design using advanced strained devices.

Original languageEnglish
Pages (from-to)284-290
Number of pages7
JournalIEEE Transactions on Electron Devices
Issue number2
StatePublished - 23 Jan 2009


  • CMOS
  • DC gain
  • Device mismatch
  • Linearity
  • Low-frequency noise
  • Process-induced strain
  • Transconductance to drain-current ratio
  • Uniaxial strained PMOSFET

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