A comparison of plasma-induced damage on the reliability between high-k/metal-gate and SiO2/poly-gate complementary metal oxide semiconductor technology

Wu Te Weng*, Yao Jen Lee, Horng-Chih Lin, Tiao Yuan Huang

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

6 Scopus citations

Abstract

This study examines the effects of plasma-induced damage (PID) both on advanced SiO2/poly-gate and Hf-based high-k/dual metal-gates transistors processed with advanced complementary metal-oxide-semiconductor (CMOS) technology. In addition to the gate dielectric degradations, this study demonstrates the PID impacts on transistor reliability including the positive bias temperature instability (PBTI) of n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) and the negative bias temperature instability (NBTI) of p-channel MOSFETs with gate dielectric thickness scaling. This study shows that high-k/metal-gate transistors are more robust against PID than conventional SiO2/poly-gate transistors with similar physical thickness. Finally this study proposes a model that successfully explains the observed experimental trends in the presence of PID for advanced high-k/metal-gate CMOS technology.

Original languageEnglish
Pages (from-to)368-377
Number of pages10
JournalSolid-State Electronics
Volume54
Issue number4
DOIs
StatePublished - 1 Apr 2010

Keywords

  • High-k/metal-gate MOSFET
  • NBTI
  • PBTI
  • Plasma-induced damage

Fingerprint Dive into the research topics of 'A comparison of plasma-induced damage on the reliability between high-k/metal-gate and SiO<sub>2</sub>/poly-gate complementary metal oxide semiconductor technology'. Together they form a unique fingerprint.

Cite this