A comparative study of electrical characteristic on sub-10-nm double-gate MOSFETs

Yiming Li*, Hong Mu Chou

*Corresponding author for this work

Research output: Contribution to journalArticle

49 Scopus citations

Abstract

We explore the structure effect on electrical characteristics of sub-10-nm double-gate metal-oxide-semiconductor field-effect transistors (DG MOSFETs). To quantitatively assess the nanoscale DG MOSFETs' characteristics, the on/off current ratio, subthreshold swing, threshold voltage (Vt h), and drain-induced barrier-height lowering are numerically calculated for the device with different channel length (L) and the thickness of silicon film (T s i). Based on our two-dimensional density gradient simulation, it is found that, to maintain optimal device characteristics and suppress short channel effects (SCEs) for nanoscale DG MOSFETs, Ts i should be simultaneously scaled down with respect to L. From a practical fabrication point-of-view, a DG MOSFET with ultrathin Ts i will suppress the SCE, but suffers the fabrication process and on-state current issues. Simulation results suggest that L/Ts i ≥ 1 may provide a good alternative in eliminating SCEs of double-gate-based nanodevices.

Original languageEnglish
Pages (from-to)645-647
Number of pages3
JournalIEEE Transactions on Nanotechnology
Volume4
Issue number5
DOIs
StatePublished - Sep 2005

Keywords

  • Adaptive computation
  • Channel length
  • Density gradient drift-diffusion model
  • Double-gate MOSFET
  • Drain-induced barrier height lowering
  • Numerical simulation
  • On/off current ratio
  • Quantum correction transport model
  • Sub 10 nm
  • Subthreshold swing

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