TY - GEN
T1 - A comparative analysis of tunneling FET circuit switching characteristics and SRAM stability and performance
AU - Chen, Yin Nien
AU - Fan, Ming Long
AU - Hu, Pi Ho
AU - Tsai, Ming Fu
AU - Pao, Chia Hao
AU - Su, Pin
AU - Chuang, Ching Te
PY - 2012/12/11
Y1 - 2012/12/11
N2 - With steep sub-threshold slope, tunneling FETs (TFETs) are promising candidates for ultra-low voltage operation, achieving low leakage current and superior performance compared with the conventional MOSFETs. However, the broad soft transition region in the Id-Vgs characteristics, where Id increases slowly to reach saturation following the steep slope region, results in large crossover region/current in an inverter, thus degrading the Hold/Read Static Noise Margin (H/RSNM) of TFET SRAMs. The Write-ability and Write Static Noise Margin (WSNM) of TFET SRAMs are constrained by the uni-directional conduction characteristics caused by the asymmetric source-drain structure and large cross-over contention of the Write access transistor and the holding transistor. In this paper, we present a detailed analysis of TFET circuit switching characteristics/ performance and compare the stability/performance of several TFET SRAM cells using atomistic TCAD mixed-mode simulations. A robust 7T Driver-Less (DL) TFET SRAM cell is proposed. The proposed 7T DL TFET SRAM cell, with decoupled Read current path from cell storage node and push-pull Write action with asymmetrical raised-cell-virtual-ground Write-assist, provides significant improvement in Read/Write stability and performance.
AB - With steep sub-threshold slope, tunneling FETs (TFETs) are promising candidates for ultra-low voltage operation, achieving low leakage current and superior performance compared with the conventional MOSFETs. However, the broad soft transition region in the Id-Vgs characteristics, where Id increases slowly to reach saturation following the steep slope region, results in large crossover region/current in an inverter, thus degrading the Hold/Read Static Noise Margin (H/RSNM) of TFET SRAMs. The Write-ability and Write Static Noise Margin (WSNM) of TFET SRAMs are constrained by the uni-directional conduction characteristics caused by the asymmetric source-drain structure and large cross-over contention of the Write access transistor and the holding transistor. In this paper, we present a detailed analysis of TFET circuit switching characteristics/ performance and compare the stability/performance of several TFET SRAM cells using atomistic TCAD mixed-mode simulations. A robust 7T Driver-Less (DL) TFET SRAM cell is proposed. The proposed 7T DL TFET SRAM cell, with decoupled Read current path from cell storage node and push-pull Write action with asymmetrical raised-cell-virtual-ground Write-assist, provides significant improvement in Read/Write stability and performance.
UR - http://www.scopus.com/inward/record.url?scp=84870607488&partnerID=8YFLogxK
U2 - 10.1109/ESSDERC.2012.6343357
DO - 10.1109/ESSDERC.2012.6343357
M3 - Conference contribution
AN - SCOPUS:84870607488
SN - 9781467317078
T3 - European Solid-State Device Research Conference
SP - 157
EP - 160
BT - 2012 Proceedings of the European Solid-State Device Research Conference, ESSDERC 2012
Y2 - 17 September 2012 through 21 September 2012
ER -