A compact software-controlled clock multiplier for SoC application

Pao Lung Chen*, Chen-Yi Lee

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

Abstract

A compact software-controlled clock multiplier for SoC application is presented in this paper. The control mechanism of clock multiplier includes frequency acquisition, phase acquisition and phase/frequency maintenance modes; these operations sequence are programmable. Our proposed clock multiplier is integrated with an 8-bit microcontroller in order to verify the proposed software-controlled mechanism. The control mechanism is sharing with the computing power of microcontroller. A proto-type chip has been implemented with 0.35um 1P4M CMOS process that can operate from 25MHz to 80MHz. The multiplication factor can range from 2 to 128 and software instructions are less than 90 instructions. Thus it not only reduces the cost and design complexity of clock multiplier, but also offers particular advantages, especially when computing power is already available.

Original languageEnglish
StatePublished - 1 Dec 2002
Event2002 45th Midwest Symposium on Circuits and Systems - Tulsa, OK, United States
Duration: 4 Aug 20027 Aug 2002

Conference

Conference2002 45th Midwest Symposium on Circuits and Systems
CountryUnited States
CityTulsa, OK
Period4/08/027/08/02

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