A compact software-controlled clock multiplier for SoC application is presented in this paper. The control mechanism of clock multiplier includes frequency acquisition, phase acquisition and phase/frequency maintenance modes; these operations sequence are programmable. Our proposed clock multiplier is integrated with an 8-bit microcontroller in order to verify the proposed software-controlled mechanism. The control mechanism is sharing with the computing power of microcontroller. A proto-type chip has been implemented with 0.35um 1P4M CMOS process that can operate from 25MHz to 80MHz. The multiplication factor can range from 2 to 128 and software instructions are less than 90 instructions. Thus it not only reduces the cost and design complexity of clock multiplier, but also offers particular advantages, especially when computing power is already available.
|State||Published - 1 Dec 2002|
|Event||2002 45th Midwest Symposium on Circuits and Systems - Tulsa, OK, United States|
Duration: 4 Aug 2002 → 7 Aug 2002
|Conference||2002 45th Midwest Symposium on Circuits and Systems|
|Period||4/08/02 → 7/08/02|