A compact on-chip ECC for low cost flash memories

Toru Tanzawa*, Tomoharu Tanaka, Ken Takeuchi, Riichiro Shirota, Seiichi Aritome, Hiroshi Watanabe, Gertjan Hemink, Kazuhiro Shimizu, Shinji Sato, Yuji Takeuchi, Kazunori Ohuchi

*Corresponding author for this work

Research output: Contribution to journalArticle

41 Scopus citations

Abstract

A compact on-chip error correcting circuit (ECC) for low cost Flash memories has been developed. The total increase in chip area is 2%, including all cells, sense amplifiers, logic, and wiring associated with the ECC. The proposed on-chip ECC, employing 10 check bits for 512 data bits, has been implemented on an experimental 64M-bit NAND Flash memory. The cumulative sector error rate has been improved from 10-4 to 10-10. By transferring read data from the sense amplifiers to the ECC twice, 522-Byte temporary buffers, which are required for the conventional ECC and occupy a large part of the ECC area, have been eliminated. As a result, the area for the circuit has been drastically reduced by a factor of 25. The proposed on-chip ECC has been optimized in consideration of balance between the reliability improvement and the cell area overhead. The power increase has been suppressed to less than 1 mA.

Original languageEnglish
Pages (from-to)662-668
Number of pages7
JournalIEEE Journal of Solid-State Circuits
Volume32
Issue number5
DOIs
StatePublished - 1 Jan 1997

Keywords

  • Cumulative error rate
  • Flash memory
  • On-chip ECC
  • Reliability improvement

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