A compact on-chip ECC for low cost flash memories

Toru Tanzawa; Tomoharu Tanaka; Ken Takeuchi; Riichiro Shirota; Seiichi Aritome; Hiroshi Watanabe; Gertjan Hemink; Kazuhiro Shimizu; Shinji Sato; Yuji Takeuchi; Kazunori Ohuchi

doi:10.1109/4.568829

A compact on-chip ECC for low cost flash memories

Toru Tanzawa^*, Tomoharu Tanaka, Ken Takeuchi, Riichiro Shirota, Seiichi Aritome, Hiroshi Watanabe, Gertjan Hemink, Kazuhiro Shimizu, Shinji Sato, Yuji Takeuchi, Kazunori Ohuchi

^*Corresponding author for this work

Department of Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

42 Scopus citations

Abstract

A compact on-chip error correcting circuit (ECC) for low cost Flash memories has been developed. The total increase in chip area is 2%, including all cells, sense amplifiers, logic, and wiring associated with the ECC. The proposed on-chip ECC, employing 10 check bits for 512 data bits, has been implemented on an experimental 64M-bit NAND Flash memory. The cumulative sector error rate has been improved from 10^-4 to 10^-10. By transferring read data from the sense amplifiers to the ECC twice, 522-Byte temporary buffers, which are required for the conventional ECC and occupy a large part of the ECC area, have been eliminated. As a result, the area for the circuit has been drastically reduced by a factor of 25. The proposed on-chip ECC has been optimized in consideration of balance between the reliability improvement and the cell area overhead. The power increase has been suppressed to less than 1 mA.

Original language	English
Pages (from-to)	662-668
Number of pages	7
Journal	IEEE Journal of Solid-State Circuits
Volume	32
Issue number	5
DOIs	https://doi.org/10.1109/4.568829
State	Published - 1 Jan 1997

Keywords

Cumulative error rate
Flash memory
On-chip ECC
Reliability improvement

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title = "A compact on-chip ECC for low cost flash memories",

abstract = "A compact on-chip error correcting circuit (ECC) for low cost Flash memories has been developed. The total increase in chip area is 2%, including all cells, sense amplifiers, logic, and wiring associated with the ECC. The proposed on-chip ECC, employing 10 check bits for 512 data bits, has been implemented on an experimental 64M-bit NAND Flash memory. The cumulative sector error rate has been improved from 10-4 to 10-10. By transferring read data from the sense amplifiers to the ECC twice, 522-Byte temporary buffers, which are required for the conventional ECC and occupy a large part of the ECC area, have been eliminated. As a result, the area for the circuit has been drastically reduced by a factor of 25. The proposed on-chip ECC has been optimized in consideration of balance between the reliability improvement and the cell area overhead. The power increase has been suppressed to less than 1 mA.",

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A compact on-chip ECC for low cost flash memories. / Tanzawa, Toru; Tanaka, Tomoharu; Takeuchi, Ken; Shirota, Riichiro; Aritome, Seiichi; Watanabe, Hiroshi; Hemink, Gertjan; Shimizu, Kazuhiro; Sato, Shinji; Takeuchi, Yuji; Ohuchi, Kazunori.

In: IEEE Journal of Solid-State Circuits, Vol. 32, No. 5, 01.01.1997, p. 662-668.

Research output: Contribution to journal › Article › peer-review

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AU - Tanzawa, Toru

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AU - Shirota, Riichiro

AU - Aritome, Seiichi

AU - Watanabe, Hiroshi

AU - Hemink, Gertjan

AU - Shimizu, Kazuhiro

AU - Sato, Shinji

AU - Takeuchi, Yuji

AU - Ohuchi, Kazunori

PY - 1997/1/1

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N2 - A compact on-chip error correcting circuit (ECC) for low cost Flash memories has been developed. The total increase in chip area is 2%, including all cells, sense amplifiers, logic, and wiring associated with the ECC. The proposed on-chip ECC, employing 10 check bits for 512 data bits, has been implemented on an experimental 64M-bit NAND Flash memory. The cumulative sector error rate has been improved from 10-4 to 10-10. By transferring read data from the sense amplifiers to the ECC twice, 522-Byte temporary buffers, which are required for the conventional ECC and occupy a large part of the ECC area, have been eliminated. As a result, the area for the circuit has been drastically reduced by a factor of 25. The proposed on-chip ECC has been optimized in consideration of balance between the reliability improvement and the cell area overhead. The power increase has been suppressed to less than 1 mA.

AB - A compact on-chip error correcting circuit (ECC) for low cost Flash memories has been developed. The total increase in chip area is 2%, including all cells, sense amplifiers, logic, and wiring associated with the ECC. The proposed on-chip ECC, employing 10 check bits for 512 data bits, has been implemented on an experimental 64M-bit NAND Flash memory. The cumulative sector error rate has been improved from 10-4 to 10-10. By transferring read data from the sense amplifiers to the ECC twice, 522-Byte temporary buffers, which are required for the conventional ECC and occupy a large part of the ECC area, have been eliminated. As a result, the area for the circuit has been drastically reduced by a factor of 25. The proposed on-chip ECC has been optimized in consideration of balance between the reliability improvement and the cell area overhead. The power increase has been suppressed to less than 1 mA.

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A compact on-chip ECC for low cost flash memories

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Keywords

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