A compact model for electrostatic discharge protection nanoelectronics simulation

Hung Mu Chou, Shao Ming Yu, Jam Wem Lee, Yi-Ming Li*

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

Abstract

In nanoelectronics, snapback phenomena play an important role in electrostatic discharge (BSD) protection devices, in particular for gigascale, very large scale integration (VLSI) circuit design. In this paper we present a new BSD equivalent circuit model for deep submicrion and nanoscale semiconductor device simulation. By considering the geometry effect in the formulation of snapback characteristics, our model can be directly incorporated into electronic circuit simulation for the whole chip BSD protection circuit design. With the developed BSD model, we can investigate robust enhancement problems and perform a SPICE based whole chip BSD protection circuit design in nanoelectronics.

Original languageAmerican English
Pages (from-to)226-238
Number of pages13
JournalInternational Journal of Nanotechnology
Volume2
Issue number3
DOIs
StatePublished - 11 Nov 2005

Keywords

  • ESD modelling
  • Geometry effect
  • Nanoelectronics
  • SPICE simulation
  • Whole chip design

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