A compact high-speed low-power rail-to-rail buffer amplifier for step-pulse signals

Chih Wen Lu*, Ching Min Hsiao

*Corresponding author for this work

Research output: Contribution to journalArticle

1 Scopus citations

Abstract

A compact high-speed low-power rail-to-rail buffer amplifier, which is suitable for driving heavy capacitive loads, is proposed. The buffer amplifier is composed of a pair of push-pull output transistors with two feedback loops consisting of a pair of complementary error amplifiers and a pair of complementary common-source amplifiers. The buffer draws little current while static but has a large driving capability while transient. A mutual bias scheme is also proposed to reduce the power consumption and the die area for LCD applications. An experimental prototype buffer amplifier implemented in a 0.35 μm CMOS technology demonstrates that the settling time is 1.5 μs for a voltage swing of 0.1 ∼ (VDD0.1) V under a 600 pF capacitance load. Quiescent current of 4 μA is measured. The area of this buffer is 32 × 109 μm2.

Original languageEnglish
Pages (from-to)1181-1197
Number of pages17
JournalJournal of Circuits, Systems and Computers
Volume19
Issue number6
DOIs
StatePublished - Oct 2010

Keywords

  • buffer amplifier
  • complementary common-source amplifier
  • error amplifier
  • LCD
  • Rail-to-rail

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