A compact DSP core with static floating-point unit & its microcode generation

Tay Jyi Lin; Hung Yueh Lin; Chie Min Chao; Chih-Wei Liu; Chein Wei Jen

doi:10.1145/988952.988966

A compact DSP core with static floating-point unit & its microcode generation

Tay Jyi Lin^*, Hung Yueh Lin, Chie Min Chao, Chih-Wei Liu, Chein Wei Jen

^*Corresponding author for this work

Department of Electronics Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Scopus citations

Abstract

The multimedia SoC usually integrates programmable digital signal processors (DSP) to accelerate data-intensive computations. But the DSP and the host processor (e.g. ARM) are both designed for standalone uses, and they must have overlapped functionalities and thus some redundant components. In this paper, we propose a compact DSP core for dual-core multimedia SoC and its complete software development tools. The DSP core contains a dataflow engine that is composed of off-the-shelf memory modules with limited ports, and we have investigated software techniques extensively to reduce the hardware complexity as the principles of VLIW processors. Moreover, the DSP is equipped with novel static floating-point units to emulate expensive floating-point DSP operations at low cost. In our experiments, this core has about thrice the performance (estimated in execution cycles) of Analog Devices ADSP-218x with similar computing resources. Our first prototype in the 0.35μm CMOS technology operates at 100MHz and consumes 122mW power. The core size is 2.8mm² including an embedded DMA controller and the AMBA AHB interface.

Original language	English
Title of host publication	Proceedings of the 2004 ACM Great Lakes Symposium on VLSI, GLSVLSI 2004
Subtitle of host publication	VLSI in the Nanometer Era
Pages	57-60
Number of pages	4
DOIs	https://doi.org/10.1145/988952.988966
State	Published - 28 Jun 2004
Event	Proceedings of the 2004 ACM Great lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era - Boston, MA, United States Duration: 26 Apr 2004 → 28 Apr 2004

Publication series

Name	Proceedings of the ACM Great Lakes Symposium on VLSI

Conference

Conference	Proceedings of the 2004 ACM Great lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era
Country	United States
City	Boston, MA
Period	26/04/04 → 28/04/04

Keywords

DSP core
Digital signal processor
Floating-point units

Access to Document

10.1145/988952.988966

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Lin, T. J., Lin, H. Y., Chao, C. M., Liu, C-W., & Jen, C. W. (2004). A compact DSP core with static floating-point unit & its microcode generation. In Proceedings of the 2004 ACM Great Lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era (pp. 57-60). (Proceedings of the ACM Great Lakes Symposium on VLSI). https://doi.org/10.1145/988952.988966

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title = "A compact DSP core with static floating-point unit & its microcode generation",

abstract = "The multimedia SoC usually integrates programmable digital signal processors (DSP) to accelerate data-intensive computations. But the DSP and the host processor (e.g. ARM) are both designed for standalone uses, and they must have overlapped functionalities and thus some redundant components. In this paper, we propose a compact DSP core for dual-core multimedia SoC and its complete software development tools. The DSP core contains a dataflow engine that is composed of off-the-shelf memory modules with limited ports, and we have investigated software techniques extensively to reduce the hardware complexity as the principles of VLIW processors. Moreover, the DSP is equipped with novel static floating-point units to emulate expensive floating-point DSP operations at low cost. In our experiments, this core has about thrice the performance (estimated in execution cycles) of Analog Devices ADSP-218x with similar computing resources. Our first prototype in the 0.35μm CMOS technology operates at 100MHz and consumes 122mW power. The core size is 2.8mm2 including an embedded DMA controller and the AMBA AHB interface.",

keywords = "DSP core, Digital signal processor, Floating-point units",

author = "Lin, {Tay Jyi} and Lin, {Hung Yueh} and Chao, {Chie Min} and Chih-Wei Liu and Jen, {Chein Wei}",

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Lin, TJ, Lin, HY, Chao, CM, Liu, C-W & Jen, CW 2004, A compact DSP core with static floating-point unit & its microcode generation. in Proceedings of the 2004 ACM Great Lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era. Proceedings of the ACM Great Lakes Symposium on VLSI, pp. 57-60, Proceedings of the 2004 ACM Great lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era, Boston, MA, United States, 26/04/04. https://doi.org/10.1145/988952.988966

A compact DSP core with static floating-point unit & its microcode generation. / Lin, Tay Jyi; Lin, Hung Yueh; Chao, Chie Min; Liu, Chih-Wei; Jen, Chein Wei.

Proceedings of the 2004 ACM Great Lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era. 2004. p. 57-60 (Proceedings of the ACM Great Lakes Symposium on VLSI).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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