A CMOS ratio-independent and gain-insensitive algorithmic analog-to-digital converter

Shu Yuan Chin*, Chung-Yu Wu

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

18 Scopus citations

Abstract

This paper describes the design of a CMOS capacitor-ratio-independent and gain-insensitive algorithmic analog-to-digital (A/D) converter. Using the fully differential switched-capacitor technique, the A/D converter is insensitive to capacitor-ratio accuracy as well as finite gain and offset voltage of operational amplifiers. The switch-induced error voltage becomes the only major error source, which is further suppressed by the fully differential structure. The proposed A/D converter is designed and fabricated by 0.8 μm double-poly double-metal CMOS technology. The op-amp gain is only 60 dB and no special layout care is done for capacitor matching. Experimental results have shown that 14-b resolution at the sampling frequency of 10 kHz can be achieved in the fabricated A/D converter. Thus it can be used in the applications which require low-cost high-resolution A/D conversion.

Original languageEnglish
Pages (from-to)1201-1207
Number of pages7
JournalIEEE Journal of Solid-State Circuits
Volume31
Issue number8
DOIs
StatePublished - 1 Aug 1996

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