A CMOS 8-bit 1.6 -GS/s DAC with digital random return-to-zero

Wei Hsin Tseng*, Jieh-Tsorng Wu, Yung Cheng Chu

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

32 Scopus citations

Abstract

A digital random return-to-zero technique is presented to improve the dynamic performance of current-steering digital-to-analog converters (DACs). To demonstrate the proposed technique, a CMOS 8-bit 1.6-GS/s DAC was fabricated in a 90-nm CMOS technology. The DAC achieves a spurious-free dynamic range better than 60 dB for a sine-wave input up to 460 MHz and better than 55 dB up to 800 MHz. The DAC consumes 90 mW of power.

Original languageEnglish
Article number5672588
Pages (from-to)1-5
Number of pages5
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume58
Issue number1
DOIs
StatePublished - 1 Jan 2011

Keywords

  • Current steering
  • digital random return-to-zero (DRRZ)
  • digital-to-analog converter (DAC)
  • return-to-zero (RZ)

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