A digital random return-to-zero technique is presented to improve the dynamic performance of current-steering digital-to-analog converters (DACs). To demonstrate the proposed technique, a CMOS 8-bit 1.6-GS/s DAC was fabricated in a 90-nm CMOS technology. The DAC achieves a spurious-free dynamic range better than 60 dB for a sine-wave input up to 460 MHz and better than 55 dB up to 800 MHz. The DAC consumes 90 mW of power.
|Number of pages||5|
|Journal||IEEE Transactions on Circuits and Systems I: Regular Papers|
|State||Published - 1 Jan 2011|
- Current steering
- digital random return-to-zero (DRRZ)
- digital-to-analog converter (DAC)
- return-to-zero (RZ)