A CMOS 6-mW 10-bit 100-MS/s two-step ADC

Yung Hui Chung*, Jieh-Tsorng Wu

*Corresponding author for this work

Research output: Contribution to journalArticle

9 Scopus citations

Abstract

A 10-bit 100-MS/s two-step ADC was fabricated using a 90 nm CMOS technology. To reduce power consumption, the ADC uses latch-type comparators for signal digitalization and an open-loop amplifier for residue amplification. The accuracy of the comparators is improved by offset calibration. The gain accuracy and the linearity of the residue amplifier are enhanced by digital background calibration. The ADC consumes 6 mW from a 1 V supply. Measured SNR and SFDR are 58.2 dB and 75 dB respectively. Measured ENOB is 9.34 bits. The FOM is 100 fJ · per conversion-step.

Original languageEnglish
Article number5607248
Pages (from-to)2217-2226
Number of pages10
JournalIEEE Journal of Solid-State Circuits
Volume45
Issue number11
DOIs
StatePublished - 1 Nov 2010

Keywords

  • Analog-digital conversion
  • calibration
  • comparators (circuits)
  • subranging ADC
  • two-step ADC

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