A CMOS 6-bit 16-GS/s time-interleaved ADC with digital background calibration

Chun Cheng Huang; Chung Yi Wang; Jieh-Tsorng Wu

doi:10.1109/VLSIC.2010.5560312

A CMOS 6-bit 16-GS/s time-interleaved ADC with digital background calibration

Chun Cheng Huang^*, Chung Yi Wang, Jieh-Tsorng Wu

^*Corresponding author for this work

Department of Electronics Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

22 Scopus citations

Abstract

An 8-channel 6-bit 16-GS/s time-interleaved ADC was fabricated using a 65nm CMOS technology. Each A/D channel is a flash ADC using latch-type comparator with background offset calibration. Timing skews among the channels are also continuously calibrated in the background. The chip achieves 42.3dB SFDR and 30.8dB SNDR at 16 GS/s sampling rate.

Original language	English
Title of host publication	2010 Symposium on VLSI Circuits, VLSIC 2010
Pages	159-160
Number of pages	2
DOIs	https://doi.org/10.1109/VLSIC.2010.5560312
State	Published - 22 Oct 2010
Event	2010 24th Symposium on VLSI Circuits, VLSIC 2010 - Honolulu, HI, United States Duration: 16 Jun 2010 → 18 Jun 2010

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Conference

Conference	2010 24th Symposium on VLSI Circuits, VLSIC 2010
Country	United States
City	Honolulu, HI
Period	16/06/10 → 18/06/10

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10.1109/VLSIC.2010.5560312

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title = "A CMOS 6-bit 16-GS/s time-interleaved ADC with digital background calibration",

abstract = "An 8-channel 6-bit 16-GS/s time-interleaved ADC was fabricated using a 65nm CMOS technology. Each A/D channel is a flash ADC using latch-type comparator with background offset calibration. Timing skews among the channels are also continuously calibrated in the background. The chip achieves 42.3dB SFDR and 30.8dB SNDR at 16 GS/s sampling rate.",

author = "Huang, {Chun Cheng} and Wang, {Chung Yi} and Jieh-Tsorng Wu",

year = "2010",

month = oct,

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doi = "10.1109/VLSIC.2010.5560312",

language = "English",

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booktitle = "2010 Symposium on VLSI Circuits, VLSIC 2010",

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}

Huang, CC, Wang, CY & Wu, J-T 2010, A CMOS 6-bit 16-GS/s time-interleaved ADC with digital background calibration. in 2010 Symposium on VLSI Circuits, VLSIC 2010., 5560312, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp. 159-160, 2010 24th Symposium on VLSI Circuits, VLSIC 2010, Honolulu, HI, United States, 16/06/10. https://doi.org/10.1109/VLSIC.2010.5560312

A CMOS 6-bit 16-GS/s time-interleaved ADC with digital background calibration. / Huang, Chun Cheng; Wang, Chung Yi; Wu, Jieh-Tsorng.

2010 Symposium on VLSI Circuits, VLSIC 2010. 2010. p. 159-160 5560312 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - An 8-channel 6-bit 16-GS/s time-interleaved ADC was fabricated using a 65nm CMOS technology. Each A/D channel is a flash ADC using latch-type comparator with background offset calibration. Timing skews among the channels are also continuously calibrated in the background. The chip achieves 42.3dB SFDR and 30.8dB SNDR at 16 GS/s sampling rate.

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A CMOS 6-bit 16-GS/s time-interleaved ADC with digital background calibration

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