@inproceedings{28f029c56916495e976c7ca5eb33e087,
title = "A CMOS 6-bit 16-GS/s time-interleaved ADC with digital background calibration",
abstract = "An 8-channel 6-bit 16-GS/s time-interleaved ADC was fabricated using a 65nm CMOS technology. Each A/D channel is a flash ADC using latch-type comparator with background offset calibration. Timing skews among the channels are also continuously calibrated in the background. The chip achieves 42.3dB SFDR and 30.8dB SNDR at 16 GS/s sampling rate.",
author = "Huang, {Chun Cheng} and Wang, {Chung Yi} and Jieh-Tsorng Wu",
year = "2010",
month = oct,
day = "22",
doi = "10.1109/VLSIC.2010.5560312",
language = "English",
isbn = "9781424476367",
series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",
pages = "159--160",
booktitle = "2010 Symposium on VLSI Circuits, VLSIC 2010",
note = "null ; Conference date: 16-06-2010 Through 18-06-2010",
}