A CMOS 6-bit 16-GS/s time-interleaved ADC with digital background calibration

Chun Cheng Huang*, Chung Yi Wang, Jieh-Tsorng Wu

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

22 Scopus citations

Abstract

An 8-channel 6-bit 16-GS/s time-interleaved ADC was fabricated using a 65nm CMOS technology. Each A/D channel is a flash ADC using latch-type comparator with background offset calibration. Timing skews among the channels are also continuously calibrated in the background. The chip achieves 42.3dB SFDR and 30.8dB SNDR at 16 GS/s sampling rate.

Original languageEnglish
Title of host publication2010 Symposium on VLSI Circuits, VLSIC 2010
Pages159-160
Number of pages2
DOIs
StatePublished - 22 Oct 2010
Event2010 24th Symposium on VLSI Circuits, VLSIC 2010 - Honolulu, HI, United States
Duration: 16 Jun 201018 Jun 2010

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers

Conference

Conference2010 24th Symposium on VLSI Circuits, VLSIC 2010
CountryUnited States
CityHonolulu, HI
Period16/06/1018/06/10

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