A CMOS 6-Bit 16-GS/s time-interleaved ADC using digital background calibration techniques

Chun Cheng Huang*, Chung Yi Wang, Jieh-Tsorng Wu

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

87 Scopus citations


An 8-channel 6-bit 16-GS/s time-interleaved analog- to-digital converter (TI ADC) was fabricated using a 65 nm CMOS technology. Each analog-to-digital channel is a 6-bit flash ADC. Its comparators are latches without the preamplifiers. The input-referred offsets of the latches are reduced by digital offset calibration. The TI ADC includes a multi-phase clock generator that uses a delay-locked loop to generate 8 sampling clocks from a reference clock of the same frequency. The uniformity of the sampling intervals is ensured by digital timing-skew calibration. Both the offset calibration and the timing-skew calibration run continuously in the background. At 16 GS/s sampling rate, this ADC chip achieves a signal-to-distortion-plus-noise ratio (SNDR) of 30.8 dB. The chip consumes 435 mW from a 1.5 V supply. The ADC active area is 0.93 × 1.58 mm2.

Original languageEnglish
Article number5728869
Pages (from-to)848-858
Number of pages11
JournalIEEE Journal of Solid-State Circuits
Issue number4
StatePublished - 1 Apr 2011


  • Analog-digital conversion
  • calibration
  • clocks
  • comparators
  • flash ADC
  • offset
  • time interleaving
  • time-interleaved ADC
  • timing circuits
  • timing skew

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