A CMOS 5.37-mW 10-Bit 200-MS/s dual-path pipelined ADC

Yun Chai*, Jieh-Tsorng Wu

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

2 Scopus citations

Abstract

A 10-bit 200-MS/s pipelined ADC was fabricated using a standard 65 nm CMOS technology. We propose a dual-path amplification technique for residue generation. We split the pipeline stage into a coarse-stage multiplying digital-to-analog converter (MDAC) and a fine-stage MDAC. The opamps for these two MDACs require different specifications. They can be designed and optimized separately. They are turned off when not in use to save power. We modify the operation of a pipeline stage to accommodate the dual-path scheme by using time-interleaving capacitor sets. Operating at 200 MS/s sampling rate, this ADC consumes 5.37 mW from a 1 V supply. It achieves a signal-to-noise-plus- distortion ratio (SNDR) better than 55 dB SNDR over the entire Nyquist band. The chip active area is 0.19 mm 2 .

Original languageEnglish
Article number6392245
Pages (from-to)2905-2915
Number of pages11
JournalIEEE Journal of Solid-State Circuits
Volume47
Issue number12
DOIs
StatePublished - 1 Dec 2012

Keywords

  • Analog-to-digital conversion
  • pipeline processing
  • switched-capacitor amplification
  • switching circuits

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