A high-speed high-resolution sample-and-hold amplifier (SHA) is designed for time-interleaved analog-to-digital converter applications. Using the techniques of precharging and output capacitor coupling can mitigate the stringent performance requirements for the opamp, resulting in low power dissipation. Implemented in a standard 0.25 μm CMOS technology, the SHA achieves 80 dB spurious-free dynamic range (SFDR) for a 1.8 Vpp output at 100 MHz Nyquist sampling rate. The SHA occupies a die area of 0.35 mm2 and dissipates 33 mW from a single 2.5 V supply.
|Number of pages||4|
|State||Published - 1 Oct 2003|
|Event||2003 Symposium on VLSI Circuits - Kyoto, Japan|
Duration: 12 Jun 2003 → 14 Jun 2003
|Conference||2003 Symposium on VLSI Circuits|
|Period||12/06/03 → 14/06/03|