A CMOS 33-mW 100-MHz 80-dB SFDR Sample-and-Hold Amplifier

Cheng Chung Hsu*, Jieh-Tsorng Wu

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

7 Scopus citations

Abstract

A high-speed high-resolution sample-and-hold amplifier (SHA) is designed for time-interleaved analog-to-digital converter applications. Using the techniques of precharging and output capacitor coupling can mitigate the stringent performance requirements for the opamp, resulting in low power dissipation. Implemented in a standard 0.25 μm CMOS technology, the SHA achieves 80 dB spurious-free dynamic range (SFDR) for a 1.8 Vpp output at 100 MHz Nyquist sampling rate. The SHA occupies a die area of 0.35 mm2 and dissipates 33 mW from a single 2.5 V supply.

Original languageEnglish
Pages263-266
Number of pages4
DOIs
StatePublished - 1 Oct 2003
Event2003 Symposium on VLSI Circuits - Kyoto, Japan
Duration: 12 Jun 200314 Jun 2003

Conference

Conference2003 Symposium on VLSI Circuits
CountryJapan
CityKyoto
Period12/06/0314/06/03

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