A CMOS 33-mW 100-MHz 80-dB SFDR Sample-and-Hold Amplifier

Cheng Chung Hsu*, Jieh-Tsorng Wu

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

3 Scopus citations

Abstract

A high-speed high-resolution sample-and-hold amplifier (SHA) is designed for time-interleaved analog-to-digital converter applications. Using the techniques of precharging and output capacitor coupling can mitigate the stringent performance requirements for the opamp, resulting in low power dissipation. Implemented in a standard 0.25μm CMOS technology, the SHA achieves 80 dB spurious-free dynamic range (SFDR) for a 1.8 Vpp output at 100 MHz Nyquist sampling rate. The SHA occupies a die area of 0.35 mm2 and dissipates 33 mW from a single 2.5 V supply.

Original languageEnglish
Pages (from-to)2122-2128
Number of pages7
JournalIEICE Transactions on Electronics
VolumeE86-C
Issue number10
DOIs
StatePublished - 1 Jan 2003

Keywords

  • Sample-and-hold circuits
  • Switched-capacitor circuits
  • Time-interleaved analog-to-digital converter

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