A CMOS 15-Bit 125-MS/s time-interleaved ADC with digital background calibration

Zwei Mei Lee*, Cheng Yen Wang, Jieh-Tsorng Wu

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

A 15-bit 125-MS/s two-channel time-interleaved pipelined ADC is fabricated in a 0.18 μm CMOS technology, and achieves 91.9 dB SFDR, 69.9 dB SNDR for a 9.99 MHz input. The ADC uses a single sample-and-hold amplifier which employs a precharging circuit technique to mitigate the performance requirements for its opamp. Digital background calibration is applied to maintain the conversion linearity of each A/D channel and also correct both gain and offset mismatches between the two channels. Excluding I/O buffers, the chip occupies an area of 4.3 × 4.3 mm2 and dissipates 909 mW from a 1.8 V supply.

Original languageEnglish
Title of host publicationProceedings of the IEEE 2006 Custom Integrated Circuits Conference, CICC 2006
Pages209-212
Number of pages4
DOIs
StatePublished - 1 Dec 2006
EventIEEE 2006 Custom Integrated Circuits Conference, CICC 2006 - San Jose, CA, United States
Duration: 10 Sep 200613 Sep 2006

Publication series

NameProceedings of the Custom Integrated Circuits Conference
ISSN (Print)0886-5930

Conference

ConferenceIEEE 2006 Custom Integrated Circuits Conference, CICC 2006
CountryUnited States
CitySan Jose, CA
Period10/09/0613/09/06

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