A clock generator with cascaded dynamic frequency counting loops for wide multiplication range applications

Pao Lung Chen*, Ching Che Chung, Jyh Neng Yang, Chen-Yi Lee

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

47 Scopus citations

Abstract

This work presents a clock generator with cascaded dynamic frequency counting (DFC) loops for wide multiplication range applications. The DFC loop, which uses variable time period to estimate and tune the frequency of the digitally controlled oscillator (DCO), enhances the resolution of frequency detection. The conventional phase-frequency detector (PFD) and programmable divider are replaced with a digital arithmetic comparator and a DCO timing counter. The value in the DCO timing counter is separated into quotient and remainder vectors. A threshold region is set in the remainder vector to reduce the influence of jitter variation in frequency detection. The loop stability can be retained by cascading two DFC loops when the multiplication factor (N) is large. The proposed clock generator achieves a multiplication range from 4 to 13 888 with output peak-to-peak jitter less than 2.8% of clock period. A test chip for the proposed clock generator is fabricated in 0.18-/μm CMOS process with core area of 0.16 mm2. Power consumption is 15 mW @ 378 MHz with 1.8-V supply voltage.

Original languageEnglish
Article number1637592
Pages (from-to)1275-1285
Number of pages11
JournalIEEE Journal of Solid-State Circuits
Volume41
Issue number6
DOIs
StatePublished - 1 Jun 2006

Keywords

  • Clock generator
  • Digitally controlled oscillator (DCO)
  • Digitally controlled varactor (DCV)
  • Dynamic frequency counting (DFC)
  • Phase-locked loop (PLL)

Fingerprint Dive into the research topics of 'A clock generator with cascaded dynamic frequency counting loops for wide multiplication range applications'. Together they form a unique fingerprint.

Cite this