A clock-controlled self-stabilized voltage technique with high dynamic power reduction for portable multimedia applications

Cheng An Chien*, Ching Hwa Cheng, Jiun-In  Guo

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper proposes a clock-controlled self-stabilized voltage (CKVdd) technique to greatly reduce dynamic power consumption for portable multimedia applications. A normal CMOS circuit shows that dynamic power consumption increases proportionally to the clock frequency. CKVdd results in a lower-than-usual frequency dependency in dynamic power consumption. The proposed technique has been implemented in a multiple standard video decoder supporting JPEG, MPEG-1/2/4, and H.264 video decoding, which yields about 41% and 73% of power consumption as compared to the static CMOS implementation at 125MHz and 25MHz, respectively.

Original languageEnglish
Title of host publication1st International Conference on Green Circuits and Systems, ICGCS 2010
Pages207-210
Number of pages4
DOIs
StatePublished - 20 Sep 2010
Event1st International Conference on Green Circuits and Systems, ICGCS 2010 - Shanghai, China
Duration: 21 Jun 201023 Jun 2010

Publication series

Name1st International Conference on Green Circuits and Systems, ICGCS 2010

Conference

Conference1st International Conference on Green Circuits and Systems, ICGCS 2010
CountryChina
CityShanghai
Period21/06/1023/06/10

Keywords

  • Low power multimedia
  • Low voltage design

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    Chien, C. A., Cheng, C. H., & Guo, J-I. (2010). A clock-controlled self-stabilized voltage technique with high dynamic power reduction for portable multimedia applications. In 1st International Conference on Green Circuits and Systems, ICGCS 2010 (pp. 207-210). [5543068] (1st International Conference on Green Circuits and Systems, ICGCS 2010). https://doi.org/10.1109/ICGCS.2010.5543068