A Capacitorless Double Gate DRAM Technology for Sub-100-nm Embedded and Stand-Alone Memory Applications

Charles Kuo*, Tsu Jae King, Chen-Ming Hu

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

43 Scopus citations

Abstract

A capacitorless, asymmetric double gate DRAM (DG-DRAM) technology is presented. Its double gate, thin body structure reduces dopant fluctuation effects, off-state leakage, and disturb problems. The cell's large body coefficient amplifies small gains of body potential into increased drain current. Experimental measurements of DG-DRAM were made using recessed channel SOI n-MOSFETs. No significant degradation in programming, retention, and read behavior was observed after 1011 cycles. Cell geometry, operating voltages, and material quality should be considered for DG-DRAM in embedded and stand-alone applications. The feasibility of DG-DRAM in future high density CMOS memories depends on issues such as manufacturability, soft error reliability, and tail bit distribution.

Original languageEnglish
Pages (from-to)2408-2416
Number of pages9
JournalIEEE Transactions on Electron Devices
Volume50
Issue number12
DOIs
StatePublished - 1 Dec 2003

Keywords

  • Double-gate MOSFETs
  • DRAM
  • Floating body DRAM
  • Fully depleted
  • Scaled CMOS
  • Thin-body SOI

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