A capacitorless double-gate DRAM cell design for high density applications

Charles Kuo*, Tsu Jae King, Chen-Ming Hu

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

28 Scopus citations

Abstract

Experimental measurements and 2-D device simulation are used to investigate a capacitorless, asymmetric double-gate DRAM (DG-DRAM) design. Soft error problems are discussed. Careful attention to cell geometry and film quality results in intrinsic retention times suitable for stand-alone and embedded memories.

Original languageEnglish
Pages (from-to)843-846
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
DOIs
StatePublished - 1 Dec 2002
Event2002 IEEE International Devices Meeting (IEDM) - San Francisco, CA, United States
Duration: 8 Dec 200211 Dec 2002

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