Experimental measurements and 2-D device simulation are used to investigate a capacitorless, asymmetric double-gate DRAM (DG-DRAM) design. Soft error problems are discussed. Careful attention to cell geometry and film quality results in intrinsic retention times suitable for stand-alone and embedded memories.
|Number of pages||4|
|Journal||Technical Digest - International Electron Devices Meeting|
|State||Published - 1 Dec 2002|
|Event||2002 IEEE International Devices Meeting (IEDM) - San Francisco, CA, United States|
Duration: 8 Dec 2002 → 11 Dec 2002