A capacitorless double-gate DRAM cell

Charles Kuo*, Tsu Jae King, Chen-Ming Hu

*Corresponding author for this work

Research output: Contribution to journalLetterpeer-review

63 Scopus citations

Abstract

A capacitorless double-gate DRAM (DG-DRAM) cell is proposed in this study. Its dual gates and thin body reduce off-state leakage and disturb problems. Dopant fluctuations, which can be particularly important in high-density arrays, are avoided by using a thin, lightly doped body. The cell's large body coefficient ((dVT)/(dVBS)) transforms small gains of body potential into increased drain current. MEDICI simulations for 85°C show that a DG-DRAM cell may sustain a measurable change in drain current several hundred milliseconds after programming. These characteristics suggest that a thin body, double-gate cell is an interesting candidate for high density DRAM technologies.

Original languageEnglish
Pages (from-to)345-347
Number of pages3
JournalIEEE Electron Device Letters
Volume23
Issue number6
DOIs
StatePublished - 1 Jun 2002

Keywords

  • Double-gate MOSFETs
  • DRAM
  • Fully depleted
  • Scaled CMOS
  • Silicon-on-insulator (SOI) MOSFETs

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