A Capacitance Method to Determine the Gate-to-Drain/Source Overlap Length of MOSFET’s

T. Y. Chan; A. T. Wu; P. K. Ko; Chen-Ming Hu

doi:10.1109/EDL.1987.26626

A Capacitance Method to Determine the Gate-to-Drain/Source Overlap Length of MOSFET’s

T. Y. Chan, A. T. Wu, P. K. Ko, Chen-Ming Hu

International College of Semiconductor Technology

Research output: Contribution to journal › Article › peer-review

13 Scopus citations

Abstract

A method is described which uses accurate measurement of gate-to-drain/source overlap capacitances to determine the gate-to-drain/source overlap length for process control as well as device characterization. The method might also be a useful analytical tool in studying lateral dopant diffusion. Using this technique, the variation in overlap length of MOSFET’s in a 4-in wafer is mapped. It is found that a significant spread of the overlap exits and is attributable to the implant shadowing by the polysilicon gate.

Original language	English
Pages (from-to)	269-271
Number of pages	3
Journal	IEEE Electron Device Letters
Volume	EDL-8
Issue number	6
DOIs	https://doi.org/10.1109/EDL.1987.26626
State	Published - 1 Jan 1987

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