A built-in-self-test ∑-Δ ADC prototype

Hao-Chiao Hong*, Sheng Chuan Liang, Hong Chin Song

*Corresponding author for this work

Research output: Contribution to journalArticle

5 Scopus citations

Abstract

This paper presents a built-in-self-test (BIST) ∑-Δ ADC prototype. The BIST circuity uses the proposed modified controlled sine wave fitting (CSWF) procedure to calculate the signal power and the total-harmonic-distortion-and-noise power in time domain separately. Compared with conventional Fast Fourier Transform (FFT) analysis, neither complex CPU/DSP nor bulky memory is required. The added BIST circuitry is purely digital and the hardware overhead is as low as 11.9 K gates. A prototype comprising the second-order design-for-digital-testability ∑-Δ modulator chip and an FPGA board which implements the digital functions is used to demonstrate the effectiveness of the BIST design. Measurement results show that the SNDR difference between conventional FFT analysis and the proposed BIST design of the standard -∈6 dBFS, 1 KHz tone test is only 0.3 dB. Furthermore, the tested dynamic range values by both methods are the same. The proposed BIST implementation achieves the advantages of compact hardware, high test accuracy, and the flexibility of adjusting the stimuli which are important features for BIST applications.

Original languageEnglish
Pages (from-to)145-156
Number of pages12
JournalJournal of Electronic Testing: Theory and Applications (JETTA)
Volume25
Issue number2-3
DOIs
StatePublished - 1 Jun 2009

Keywords

  • BIST
  • Controlled sine wave fitting
  • Output response analyzer
  • ∑-Δ ADC

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