This paper presents a low-power design of a two-stream MEMO FFT/IFFT processor for WiMAX applications. A novel block scaling method and a new ping-pong cache-memory architecture are proposed to reduce the power consumption and hardware cost With these schemes, half the memory accesses and 64-Kbit memory can be saved. Furthermore, by proper scheduling of the two data streams, the proposed design achieves better hardware utilization and can process two 2048-point FFTs/IFFTs consecutively within 2052 cycles. A test chip of the proposed FFT/EFFT processor has been designed using UMC 0.13 μm 1P8M process with a core area of 1332×1590 μm2. The SQNR performance of the 2048-point FFT/EFFT is over 48 dB for QPSK and 16/64-QAM modulations. Power dissipation of two 2048-point FFT computations is about 17.26 mW at 22.86 MHz which meets the maximum throughput rate of WiMAX applications.
|Number of pages||4|
|State||Published - 1 Dec 2006|
|Event||2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006 - Hangzhou, China|
Duration: 13 Nov 2006 → 15 Nov 2006
|Conference||2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006|
|Period||13/11/06 → 15/11/06|