A block-level optimization of comprehensive thermal-aware power management for SoC integration in nano-scale CMOS technology

Wei Min Chan*, Her-Ming Chiueh

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

Modern SoC integrations and mobile systems have emphasized low power techniques due to shortage of battery life. Conventional power management designs focused on the reduction of dynamic power consumption, recent designs begin to take leakage power into consideration since it becomes an important factor in nano-scale CMOS technology. Latest development has taken advantage of modularity in SoC design methodology to develop the block-level control technique for power reductions. However, thermal gradient over the system and its impacts to SoC designs are barely discussed. In this research, a block-level optimization of comprehensive thermalaware power management is presented. The proposed design applies several low power techniques to control different power sources and handles thermal impacts to provide performance coherence. As a result, optimal power-reductions and performance coherence can be guaranteed within the whole system. The simulation results show a significant improvement in stability and leakage power reduction for most circuitries. The results are based on TSMC 100nm CMOS technology.

Original languageEnglish
Title of host publication2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005
Pages480-483
Number of pages4
DOIs
StatePublished - 1 Dec 2005
Event2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005 - Cincinnati, OH, United States
Duration: 7 Aug 200510 Aug 2005

Publication series

NameMidwest Symposium on Circuits and Systems
Volume2005
ISSN (Print)1548-3746

Conference

Conference2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005
CountryUnited States
CityCincinnati, OH
Period7/08/0510/08/05

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