A Background Timing-Skew Calibration Technique for Time-Interleaved Analog-to-Digital Converters

Chung Yi Wang, Jieh-Tsorng Wu

Research output: Contribution to journalArticle

38 Scopus citations

Abstract

This paper presents a background timing-skew calibration technique for time-interleaved analog-to-digital converters (ADCs). The timing skew between any two adjacent analog-digital (A/D) channels is detected by counting the number of zero crossings of the ADCs input while randomly alternating their sampling sequence. Digitally controlled delay units are adjusted to minimize the timing skews among the A/D channels caused by the mismatches among the clock routes. The calibration behaviors, including converging speed and timing jitter, are theoretically analyzed and verified with simulations. A 6-bit 16-channel ADC is used as an example.

Original languageEnglish
Pages (from-to)299-303
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume53
Issue number4
DOIs
StatePublished - 6 Apr 2006

Keywords

  • Analog-digital (A/D) conversion
  • calibration
  • timing

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