A 952MS/S max-log MAP decoder chip using radix-4 × 4 ACS architecture

Cheng Hao Tang*, Cheng Chi Wong, Chih Lung Chen, Chien Ching Lin, Hsie-Chia Chang

*Corresponding author for this work

Research output: Contribution to conferencePaper

21 Scopus citations

Abstract

In this paper, a high-speed Max-Log MAP decoder is presented for soft-in and soft-out trellis decoding. The high throughput is achieved with a two-dimensional ACS design on the high-radix trellis structure, resulting in a highly parallel and area-efficient decoder. We further apply the retiming technique to reduce the critical path delay of ACS operation. After 0.13μm CMOS chip implementation, the decoder occupies 1.96mm2 area containing 220K gates. The estimated timing under the 1.08V supply and the worst case corner shows that the test chip can achieve the maximum 952MS/S throughput. To our knowledge, the present Max-Log MAP decoder has the highest throughput with the modest hardware cost.

Original languageEnglish
Pages79-82
Number of pages4
DOIs
StatePublished - 1 Dec 2006
Event2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006 - Hangzhou, China
Duration: 13 Nov 200615 Nov 2006

Conference

Conference2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006
CountryChina
CityHangzhou
Period13/11/0615/11/06

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    Tang, C. H., Wong, C. C., Chen, C. L., Lin, C. C., & Chang, H-C. (2006). A 952MS/S max-log MAP decoder chip using radix-4 × 4 ACS architecture. 79-82. Paper presented at 2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006, Hangzhou, China. https://doi.org/10.1109/ASSCC.2006.357856