A 94fps view synthesis engine for HD1080p video

Fu Jen Chang*, Yu Cheng Tseng, Tian-Sheuan Chang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Scopus citations

Abstract

This paper presents a low-cost and high-throughput view synthesis engine based the view synthesis reference software (VSRS) algorithm. With the horizontal shift mode, we propose the row-based pipelined architecture to save the memory cost for original camera rotation issue. Owing to row-based method, internal Z-buffers for storing depth data can be reduced, and also the external bandwidth can be reduced. With the 90nm technology process, our view synthesis engine can achieve the throughput of 94.5 frame/sec for the HD1080p input with the gate count of 142.9k and the low memory cost of 54.72Kbytes.

Original languageEnglish
Title of host publication2011 IEEE Visual Communications and Image Processing, VCIP 2011
DOIs
StatePublished - 1 Dec 2011
Event2011 IEEE Visual Communications and Image Processing, VCIP 2011 - Tainan, Taiwan
Duration: 6 Nov 20119 Nov 2011

Publication series

Name2011 IEEE Visual Communications and Image Processing, VCIP 2011

Conference

Conference2011 IEEE Visual Communications and Image Processing, VCIP 2011
CountryTaiwan
CityTainan
Period6/11/119/11/11

Keywords

  • row-based pipelined architecture
  • virtual view synthesis

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  • Cite this

    Chang, F. J., Tseng, Y. C., & Chang, T-S. (2011). A 94fps view synthesis engine for HD1080p video. In 2011 IEEE Visual Communications and Image Processing, VCIP 2011 [6116009] (2011 IEEE Visual Communications and Image Processing, VCIP 2011). https://doi.org/10.1109/VCIP.2011.6116009