A 802.15.3c/802.11ad compliant 24 Gb/s FFT processor for 60 GHz communication systems

Henry Lopez Davila, Chun Yi Liu, Wei Chang Liu, Shen Jui Huang, Shyh Jye Jou, Sau Gee Chen

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

This paper, we present a 24 Gb/s 512-point 8X-parallel FFT processor for 60 GHz communication systems. The proposed design is a pipelined Multipath Delay Feedback (MDF) radix-23 architecture, which exploits the parallelism of the multipath scheme together with pipeline technique to achieve a high throughput rate. Besides, the proposed FFT processor is implemented with an area efficient optimized multiplier architecture that avoid the need to store the twiddle factor in memory and a dynamic scaling technique to enhance the SQNR, allowing the FFT to operate with 16-QAM and 64-QAM for single carrier (SC) and orthogonal frequency-division multiplexing(OFDM) schemes. This FFT processor has been implemented in a SC/OFDM dual-mode baseband receiver satisfying the requirements of the 802.15.3c/802.11ad standard with a 40nm CMOS process. The post-layout implementation results show that the proposed FFT processor is able to achieve up to 24 Gb/s throughput rate at 500MHz clock with a power consumption of 87mW and area of 0.64mm2.

Original languageEnglish
Title of host publicationProceedings - 28th IEEE International System on Chip Conference, SOCC 2015
EditorsThomas Buchner, Danella Zhao, Karan Bhatia, Ramalingam Sridhar
PublisherIEEE Computer Society
Pages44-48
Number of pages5
ISBN (Electronic)9781467390934
DOIs
StatePublished - 12 Feb 2016
Event28th IEEE International System on Chip Conference, SOCC 2015 - Beijing, China
Duration: 8 Sep 201511 Sep 2015

Publication series

NameInternational System on Chip Conference
Volume2016-February
ISSN (Print)2164-1676
ISSN (Electronic)2164-1706

Conference

Conference28th IEEE International System on Chip Conference, SOCC 2015
CountryChina
CityBeijing
Period8/09/1511/09/15

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