A 7mW-to-183mW dynamic quality-scalable H.264 video encoder chip

Hsiu Cheng Chang*, Jia Wei Chen, Ching Lung Su, Yao Chang Yang, Yao Li, Chun Hao Chang, Ze Min Chen, Wei Sen Yang, Chien Chang Lin, Ching Wen Chen, Jinn Shan Wang, Jiun-In  Guo

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

42 Scopus citations

Abstract

A dynamic quality-scalable H.264 video encoder is presented for power-adaptive video encoding. In 0.13μm CMOS technology, it requires 470kgates/13.3kB SRAM and consumes 7mW/183mW In encoding 30fps CIF/HD720 video. Compared to the state-of-the-art design for real-time HD720 video encoding, a 49% reduction in gate count and a 61% reduction in internal memory is achieved.

Original languageEnglish
Title of host publication2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers
DOIs
StatePublished - 27 Sep 2007
Event54th IEEE International Solid-State Circuits Conference, ISSCC 2007 - San Francisco, CA, United States
Duration: 11 Feb 200715 Feb 2007

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
ISSN (Print)0193-6530

Conference

Conference54th IEEE International Solid-State Circuits Conference, ISSCC 2007
CountryUnited States
CitySan Francisco, CA
Period11/02/0715/02/07

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