A 6Gbps serial link transmitter with pre-emphasis

Chang Min Chu*, Chih Hua Chuang, Chi Hsien Lin, Shyh-Jye Jou

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations

Abstract

In this paper, we propose a novel 6Gbps SATA transmitter, The transmitter is constructed by PISO, driver, pre-emphasis and PLL for a 1∼5 meter cable. A test chip of transmitter with PLL and on-chip termination is Implemented to verify the design methodology, The overall circuit is implemented in TSMC 0.18um 1P6M 1.8V CMOS process. The whole measured transmitter jitter is about 44ps and the power consumption is 68mW for 6Gbps case.

Original languageEnglish
Title of host publication2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers
DOIs
StatePublished - 28 Sep 2007
Event2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Hsinchu, Taiwan
Duration: 25 Apr 200727 Apr 2007

Publication series

Name2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers

Conference

Conference2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007
CountryTaiwan
CityHsinchu
Period25/04/0727/04/07

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    Chu, C. M., Chuang, C. H., Lin, C. H., & Jou, S-J. (2007). A 6Gbps serial link transmitter with pre-emphasis. In 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers [4239405] (2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers). https://doi.org/10.1109/VDAT.2007.373213