A 65nm Sub-1V multi-stage low-dropout (LDO) regulator design for SoC systems

Yu Huei Lee*, Ke-Horng Chen

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

9 Scopus citations

Abstract

This proposed 65 nm sub-1V multi-stage low-dropout (LDO) regulator aims to integrate of power management for SoC systems. The multi-stage structure can derive the high dc voltage gain from the short-channel core devices to insure the load/line regulation. The inserted flying capacitor used to separate the high-frequency non-dominant poles can increase the system phase margin. Moreover, a dynamic gain adjusting (DGA) mechanism can adjust the dc voltage gain based on the load condition to ensure the LDO operation at ultra light loads. The correct operation under sub-1V condition is achieved with 65 nm low-power core devices. Simulated load transient response shows the voltage recovery time is within 0.6 μs when load current changes from 50 μA to 100 mA and vice versa.

Original languageEnglish
Title of host publication2010 IEEE International 53rd Midwest Symposium on Circuits and Systems, MWSCAS 2010
Pages584-587
Number of pages4
DOIs
StatePublished - 20 Sep 2010
Event53rd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2010 - Seattle, WA, United States
Duration: 1 Aug 20104 Aug 2010

Publication series

NameMidwest Symposium on Circuits and Systems
ISSN (Print)1548-3746

Conference

Conference53rd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2010
CountryUnited States
CitySeattle, WA
Period1/08/104/08/10

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