A 65 nm node strained SOI technology with high performance is demonstrated, providing drive currents of 1015 and 500 μA/μm for N-FET and P-FET, respectively, at an off-state leakage of 40 nA/μm using 1 V operation. The technology employs an aggressively scaled slim spacer of 30 nm width to amplify stress benefits for performance improvement, and to reduce 10-20% layout area for SRAM-cell-like circuits, while maintaining excellent hot carrier immunity and well-controlled short-channel effects. For the first time, we demonstrate that FinFET devices, implicitly implemented in this technology, offer a 8-15% higher inverter speed compared to planar SOI devices at the same drive current.
|Number of pages||4|
|Journal||Technical Digest - International Electron Devices Meeting|
|State||Published - 1 Dec 2003|
|Event||IEEE International Electron Devices Meeting - Washington, DC, United States|
Duration: 8 Dec 2003 → 10 Dec 2003