A 65nm low power 2T1D embedded dram with leakage current reduction

Mu Tien Chang*, Po-Tsang Huang, Wei Hwang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

5 Scopus citations

Abstract

Gain cell memories feature high speed, low power, and high density, which are suitable for SoC designs. In this paper, low power techniques to reduce leakage currents for 2T1D gain cell memory array are presented. For each memory cell, p-type gated diode storage device is applied. In addition, footer power gating and foot driver are applied on each memory word. Simulation results show that the proposed 2T1D memory array structure has 97.7% and 80% standby power reduction over typical 2T1D and typical 3T1D memory array, respectively. All the simulation results are based on Predictive Technology Model (PTM) 65nm CMOS bulk technology.

Original languageEnglish
Title of host publicationProceedings - 20th Anniversary IEEE International SOC Conference
Pages207-210
Number of pages4
DOIs
StatePublished - 1 Dec 2007
Event20th Anniversary IEEE International SOC Conference - Hsinchu, Taiwan
Duration: 26 Sep 200729 Sep 2007

Publication series

NameProceedings - 20th Anniversary IEEE International SOC Conference

Conference

Conference20th Anniversary IEEE International SOC Conference
CountryTaiwan
CityHsinchu
Period26/09/0729/09/07

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