Gain cell memories feature high speed, low power, and high density, which are suitable for SoC designs. In this paper, low power techniques to reduce leakage currents for 2T1D gain cell memory array are presented. For each memory cell, p-type gated diode storage device is applied. In addition, footer power gating and foot driver are applied on each memory word. Simulation results show that the proposed 2T1D memory array structure has 97.7% and 80% standby power reduction over typical 2T1D and typical 3T1D memory array, respectively. All the simulation results are based on Predictive Technology Model (PTM) 65nm CMOS bulk technology.