A 65nm CMOS 140 GHz 27.3 dBm EIRP transmit array with membrane antenna for highly scalable multi-chip phase arrays

Adrian Tang, Nacer Chahat, Yan Zhao, Gabriel Virbila, Choonsup Lee, Frank Hsiao, Li Du, Yen-Cheng Kuan, Mau-Chung Chang, Goutam Chattopadhyay, Imran Mehdi

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

11 Scopus citations

Abstract

This paper presents a scalable transmit phase array operating at 140 GHz which employs a local PLL reference generation system. Unlike traditional CMOS phase arrays, this enables the array to be formed over multiple chips while avoiding the challenges of distributing mm-wave signals between them. The prototype chip consumes 131 mW of power and occupies 1.95 mm2 of chip area when implemented in 65 nm CMOS technology.

Original languageEnglish
Title of host publication2014 IEEE MTT-S International Microwave Symposium, IMS 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)9781479938698
DOIs
StatePublished - 1 Jan 2014
Event2014 IEEE MTT-S International Microwave Symposium, IMS 2014 - Tampa, FL, United States
Duration: 1 Jun 20146 Jun 2014

Publication series

NameIEEE MTT-S International Microwave Symposium Digest
ISSN (Print)0149-645X

Conference

Conference2014 IEEE MTT-S International Microwave Symposium, IMS 2014
CountryUnited States
CityTampa, FL
Period1/06/146/06/14

Keywords

  • Locally Synchronized PLL
  • Phased Array Transmitter

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