A 65-fJ/conversion-step 0.9-V 200-kS/s rail-to-rail 8-bit successive approximation ADC

Hao-Chiao Hong*, Guo Ming Lee

*Corresponding author for this work

Research output: Contribution to journalArticle

154 Scopus citations

Abstract

An 8-bit successive approximation (SA) analog-to-digital converter (ADC) in 0.18 μm CMOS dedicated for energy-limited applications is presented. The SA ADC achieves a wide effective resolution bandwidth (ERBW) by applying only one bootstrapped switch, thereby preserving the desired low power characteristic. Measurement results show that at a supply voltage of 0.9 V and an output rate of 200 kS/s, the SA ADC performs a peak signal-to-noise-and-distortion ratio of 47.4 dB and an ERBW up to its Nyquist bandwidth (100 kHz). It consumes 2.47 μW in the test, corresponding to a figure of merit of 65 fJ/conversion-step.

Original languageEnglish
Pages (from-to)2161-2168
Number of pages8
JournalIEEE Journal of Solid-State Circuits
Volume42
Issue number10
DOIs
StatePublished - 1 Oct 2007

Keywords

  • μW design
  • ADC
  • Energy efficient
  • Low power
  • Low supply voltage
  • Successive approximation

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