A 600-MSPS 8-bit CMOS ADC using distributed track-and-hold with complementary resistor/capacitor averaging

Zhengyu Wang*, Mau-Chung Chang

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

14 Scopus citations

Abstract

An 8-bit 600 megasamples-per-second (MSPS) analog-to-digital converter (ADC) has been implemented in 0.18-μm CMOS to achieve a minimum signal-to-noise-and-distortion ratio (SNDR) of 40 dB and a spurious-free dynamic range (SFDR) of 45 dB with input-signal bandwidth up to 200 MHz. The ADC is also capable of sampling up to 1 gigasamples/s and maintaining 39-dB SNDR at an input-signal frequency of 55 MHz. Distributed track-and-hold (DT&H) is employed at the ADC front end to relieve the linearity burden on individual T&H subunit. Complementary resistor and capacitor averaging networks are employed before and after DT&H switches separately in order to alleviate offset- and switching-induced errors, respectively. The fabricated ADC occupies 0.5 mm2 in chip area and consumes 207 mW from a 1.8-V supply.

Original languageEnglish
Pages (from-to)3621-3627
Number of pages7
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume55
Issue number11
DOIs
StatePublished - 1 Dec 2008

Keywords

  • Analog-to-digital converter (ADC)
  • Averaging
  • Distributed
  • Track-and-hold (T&H)

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