Abstract
Healthcare issues arose from population aging. Meanwhile, electrocardiogram (ECG) is a powerful measurement tool. The first step of ECG is to detect QRS complexes. A state-of-the-art QRS detection algorithm was modified and implemented to an application-specific integrated circuit (ASIC). By the dedicated architecture design, the novel ASIC is proposed with 0.68 mm 2 core area and 2.21 W power consumption. It is the smallest QRS detection ASIC based on 0.18 m technology. In addition, the sensitivity is 95.65% and the positive prediction of the ASIC is 99.36% based on the MIT/BIH arrhythmia database certification.
Original language | English |
---|---|
Article number | 809393 |
Journal | VLSI Design |
Volume | 2012 |
DOIs | |
State | Published - 26 Dec 2012 |