A 5Gb/s monolithically integrated optical receiver in standard CMOS process

Hsiang Yi Chiu*, Bin Wei Yi, Chia-Ming Tsai

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review


This paper presents a 5Gb/s monolithically integrated optical receiver, consisting of an integrated photodiode and receiver front-end circuits in a standard CMOS process. To achieve high-speed photo response for wavelengths lying between 600nm and 1000nm, an interpolation-weighting equalizer is proposed to compensate for the roll-off characteristics in the photo response of the photodiode due to the slow substrate carriers effect. At a wavelength of 850nm, the optical receiver achieves a variable transimpedance gain from 60dB Ω to 90dB Ω and the -3dB bandwidth is 2.9GHz. For a bit error rate of 10-12the measured sensitivity is -1.7dBm at 5Gb/s. The chip size is 650μmx790μm and the total power consumption is 112mW at 1.5V.

Original languageEnglish
Pages (from-to)261-268
Number of pages8
JournalInternational Journal of Electrical Engineering
Issue number3
StatePublished - 1 Jun 2009


  • CMOS photodiode
  • Equalizer
  • Optical receiver

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