A 5.7Gbps row-based layered scheduling LDPC decoder for IEEE 802.15.3c applications

Shiang Yu Hung*, Shao Wei Yen, Chih Lung Chen, Hsie-Chia Chang, Shyh-Jye Jou, Chen-Yi Lee

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Scopus citations

Abstract

A LDPC decoder chip supporting four code rates of IEEE 802.15.3c applications is presented. The row-based layered scheduling with normalized min-sum algorithm is proposed to reduce the iteration number while maintaining similar performance. In addition, the reconfigurable 8/16/32-input sorter is designed to deal with four LDPC codes. In order to alleviate routing complexity, both of the reallocation of sorter inputs and pre-coding routing network are proposed to reduce the input numbers of multiplexers by 64%. Fabricated in 65-nm 1P10M CMOS process, this test chip can achieve maximum 5.79Gbps throughput for the highest code rate code while the hardware efficiency and energy efficiency are 3.7Gbps/mm2 and 62.4pJ/bit, respectively.

Original languageEnglish
Title of host publication2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010
Pages309-312
Number of pages4
DOIs
StatePublished - 1 Dec 2010
Event2010 6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010 - Beijing, China
Duration: 8 Nov 201010 Nov 2010

Publication series

Name2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010

Conference

Conference2010 6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010
CountryChina
CityBeijing
Period8/11/1010/11/10

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    Hung, S. Y., Yen, S. W., Chen, C. L., Chang, H-C., Jou, S-J., & Lee, C-Y. (2010). A 5.7Gbps row-based layered scheduling LDPC decoder for IEEE 802.15.3c applications. In 2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010 (pp. 309-312). [5716617] (2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010). https://doi.org/10.1109/ASSCC.2010.5716617