A 57-66 GHz medium power amplifier in 65-nm CMOS technology

Chia Yu Hsieh*, Jhe Jia Kuo, Zuo-Min Tsai , Kun You Lin

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

6 Scopus citations

Abstract

This paper presents the design and measurement results of a 57-66 GHz medium power amplifier in 65-nm LP CMOS process. This amplifier is designed with broadband matching concern, which can achieve a measured gain more than 21 dB from 5766 GHz and have a 3-dB bandwidth more than 14 GHz while consuming 54 mW from a 1.2 V supply. The measured results exhibit Psat of 10.3 dBm, P1dB of 6.2 dBm, and the peak PAE is 16 %at 58 GHz. The chip size is only 0.3 mm2.

Original languageEnglish
Title of host publication2010 Asia-Pacific Microwave Conference Proceedings, APMC 2010
Pages1617-1620
Number of pages4
StatePublished - 1 Dec 2010
Event2010 Asia-Pacific Microwave Conference, APMC 2010 - Yokohama, Japan
Duration: 7 Dec 201010 Dec 2010

Publication series

NameAsia-Pacific Microwave Conference Proceedings, APMC

Conference

Conference2010 Asia-Pacific Microwave Conference, APMC 2010
CountryJapan
CityYokohama
Period7/12/1010/12/10

Keywords

  • 60 GHz
  • Broadband
  • CMOS
  • MMIC
  • power amplifiers

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