A 55nm 0.55v 6T SRAM with variation-tolerant dual-tracking word-line under-drive and data-aware write-assist

Yi Wei Lin*, Hao I. Yang, Geng Cing Lin, Chi Shin Chang, Ching Te Chuang, Wei Hwang, Chia Cheng Chen, Willis Shih, Huan Shun Huang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

7 Scopus citations

Abstract

We present a 55nm 128Kb 6T SRAM with a variation-tolerant dual-tracking Word-Line Under-Drive (WLUD) to improve the RSNM and a Data-Aware Write-Assist (DAWA) scheme. Error free full functionality without redundancy is achieved from 1.5V down to 0.55V with area overhead of 4% for WLUD and 14% for DAWA, respectively. The measured power overheads (FF, 25oC) are 1.1% for WLUD and 3.3% for DAWA at 1.0V (3% and 5.3% at 0.6V), respectively. The maximum operating frequency is 940MHz (360MHz) at 1.0V (0.6V) and 25oC. The measured power/performance (FF, 25oC) is 0.117mW/MHz (0.023mW/MHz) at 1.0V (0.6V).

Original languageEnglish
Title of host publicationISLPED'12 - Proceedings of the International Symposium on Low Power Electronics and Design
Pages79-84
Number of pages6
DOIs
StatePublished - 4 Sep 2012
Event2012 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED'12 - Redondo Beach, CA, United States
Duration: 30 Jul 20121 Aug 2012

Publication series

NameProceedings of the International Symposium on Low Power Electronics and Design
ISSN (Print)1533-4678

Conference

Conference2012 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED'12
CountryUnited States
CityRedondo Beach, CA
Period30/07/121/08/12

Keywords

  • data-aware write-assist (dawa)
  • static random access memory (sram)
  • word-line under-drive (wlud)

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