A 5.37mW 10b 200MS/s dual-path pipelined ADC

Yun Chai*, Jieh-Tsorng Wu

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

27 Scopus citations

Abstract

The opamps in a switched-capacitor (SC) pipelined ADC provide the functions of sample-and-hold, residue generation, and residue amplification [1,2]. High-performance opamps that meet the requirements for dc gain, speed, and signal range usually consume large power. We propose a scheme where the residue amplification is performed first by a coarse amplifier (CA), and then by a fine amplifier (FA). The CA generates a large-swing output that may not be accurate due to low dc gain and slow speed. Subsequently, the FA produces a small-swing output that stands as the error of the CA. The requirements for the CA and FA are different. They can be designed and optimized separately, resulting in low power dissipation. We report a 10b SC pipelined ADC to demonstrate this technique. Fabricated in 65nm CMOS, this ADC achieves 56.7dB SNDR at 200MS/s sampling rate, and consumes 5.37mW from a 1V supply.

Original languageEnglish
Title of host publication2012 IEEE International Solid-State Circuits Conference, ISSCC 2012 - Digest of Technical Papers
Pages462-463
Number of pages2
DOIs
StatePublished - 11 May 2012
Event59th International Solid-State Circuits Conference, ISSCC 2012 - San Francisco, CA, United States
Duration: 19 Feb 201223 Feb 2012

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume55
ISSN (Print)0193-6530

Conference

Conference59th International Solid-State Circuits Conference, ISSCC 2012
CountryUnited States
CitySan Francisco, CA
Period19/02/1223/02/12

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