A 5.2mW all-digital fast-lock self-calibrated multiphase delay-locked loop

Li Pu Chuang*, Ming Hung Chang, Po-Tsang Huang, Chih Hao Kan, Wei Hwang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Scopus citations

Abstract

A 333MHz-1GHz all-digital multiphase delay-locked loop with precise multi-phase output has been designed with TSMC 130nm CMOS technology model. A modified binary search algorithm is proposed to match up a linear approximate delay element (LADE). The LADE property of linearity and insensitive to PVT variations is good for digitally-controlled delay element. The lock-in time could be reduced down to 14 reference clock cycles, and enhance the operation range based on LADE/binary search algorithm co-operate effort. The timing error caused by process mismatch is further reduced by proposed rapid self-calibration (RSC) algorithm. A calibration unit is designed based on RSC algorithm, which reduces the maximum timing error to less than 9ps when DLL is operating at 500MHz. The entire calibration unit could be turned off after calibration procedure is complete to reduce power consumption. The total power dissipation of the all-digital self-calibrated multiphase delay-locked loop is 5.2mW at 1GHz with a 1.2V power supply.

Original languageEnglish
Title of host publication2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
Pages3342-3345
Number of pages4
DOIs
StatePublished - 19 Sep 2008
Event2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008 - Seattle, WA, United States
Duration: 18 May 200821 May 2008

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Conference

Conference2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
CountryUnited States
CitySeattle, WA
Period18/05/0821/05/08

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  • Cite this

    Chuang, L. P., Chang, M. H., Huang, P-T., Kan, C. H., & Hwang, W. (2008). A 5.2mW all-digital fast-lock self-calibrated multiphase delay-locked loop. In 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008 (pp. 3342-3345). [4542174] (Proceedings - IEEE International Symposium on Circuits and Systems). https://doi.org/10.1109/ISCAS.2008.4542174