A 52mW 1200MIPS compact DSP for multi-core media SoC

Shih Hao Ou*, Tay Jyi Lin, Chao Wei Huang, Yu Ting Kuo, Chie Min Chao, Chih-Wei Liu, Chein Wei Jen

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents a DSP core for multi-core media SoC, which is optimized to execute a set of signal processing tasks very efficiently. The fully-programmable core has a data-centric instruction set and a corresponding latency-insensitive micro-architecture, where the hardware design is optimized concurrently with its automatic software generator. The proposed DSP core has 3X performance (in cycles) of those found in commercial dual-core application processors with similar computing resources. The silicon implementation in UMC 0.18μm 1P6M CMOS technology operates at 314MHz and consumes only 52mW average power.

Original languageEnglish
Title of host publicationProceedings of the ASP-DAC 2006
Subtitle of host publicationAsia and South Pacific Design Automation Conference 2006
Pages118-119
Number of pages2
DOIs
StatePublished - 19 Sep 2006
EventASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006 - Yokohama, Japan
Duration: 24 Jan 200627 Jan 2006

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume2006

Conference

ConferenceASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006
CountryJapan
CityYokohama
Period24/01/0627/01/06

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    Ou, S. H., Lin, T. J., Huang, C. W., Kuo, Y. T., Chao, C. M., Liu, C-W., & Jen, C. W. (2006). A 52mW 1200MIPS compact DSP for multi-core media SoC. In Proceedings of the ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006 (pp. 118-119). [1594665] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 2006). https://doi.org/10.1109/ASPDAC.2006.1594665