A 50nA quiescent current asynchronous digital-LDO with PLL-modulated fast-DVS power management in 40nm CMOS for 5.6 times MIPS performance

Yu Huei Lee*, Shen Yu Peng, Alex Chun Hsien Wu, Chao Chang Chiu, Yao Yi Yang, Ming Hsin Huang, Ke-Horng Chen, Ying Hsi Lin, Shih Wei Wang, Ching Yuan Yeh, Chen Chih Huang, Chao Cheng Lee

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Scopus citations

Abstract

A 50nA quiescent current asynchronous digital-LDO (DLDO) integrated with the PLL-modulated switching regulator (SWR) exhibits the hybrid power management operation. The proposed bidirectional asynchronous wave pipeline (BAWP) in the asynchronous DLDO realizes the Fast-DVS (F-DVS) operation within tens of nano-seconds. The SWR with the leading phase amplifier achieves on-the-fly DVS and 94% peak efficiency, as well as improves 5.6 times MIPS performance through hybrid operation. The fabricated chip occupies 1.04mm 2 in 40nm CMOS.

Original languageEnglish
Title of host publication2012 Symposium on VLSI Circuits, VLSIC 2012
Pages178-179
Number of pages2
DOIs
StatePublished - 28 Sep 2012
Event2012 Symposium on VLSI Circuits, VLSIC 2012 - Honolulu, HI, United States
Duration: 13 Jun 201215 Jun 2012

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers

Conference

Conference2012 Symposium on VLSI Circuits, VLSIC 2012
CountryUnited States
CityHonolulu, HI
Period13/06/1215/06/12

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  • Cite this

    Lee, Y. H., Peng, S. Y., Wu, A. C. H., Chiu, C. C., Yang, Y. Y., Huang, M. H., Chen, K-H., Lin, Y. H., Wang, S. W., Yeh, C. Y., Huang, C. C., & Lee, C. C. (2012). A 50nA quiescent current asynchronous digital-LDO with PLL-modulated fast-DVS power management in 40nm CMOS for 5.6 times MIPS performance. In 2012 Symposium on VLSI Circuits, VLSIC 2012 (pp. 178-179). [6243848] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). https://doi.org/10.1109/VLSIC.2012.6243848