A 50Gb/s all-digital adaptive noise-suppression (NS) feed-forward equalizer (AFFE) and adaptive decision feedback equalizer (ADFE) for 2-level pulse amplitude modulation (2-PAM) serial link systems is presented. Based on a parallel extended incremental coefficients-lookahead scheme (EICL), we propose a Dual Data-paths Self-Lookahead Filter (DD-SLF) for ADFE. DD-SLF architecture has better energy efficiency and hardware area than an original SLF architecture due to the number of delay elements in the feedback loop is reduced. Furthermore, gated clock technique with the design idea of register file architecture is used to replace the pipelined delay elements to save power. The whole equalizer which operates at 1GHz system clock rate with 50 parallelisms is implemented in 40nm CMOS technology with a 0.38mm2 core area. The equalizer with 50Gb/s throughput rate achieves 2.6pJ/bit energy efficiency under 0.81V supply measurement results.